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80C154/83c154 rev.f (14 jan. 97) 1 matra mhs description temic's 80C154 and 83c154 are high performance cmos single chip m c. the 83c154 retains all the features of the 80c52 with extended rom capacity (16 k bytes), 256 bytes of ram, 32 i/o lines, a 6-source 2-level interrupts, a full duplex serial port, an on-chip oscillator and clock circuits, three 16 bit timers with extra features : 32 bit timer and watchdog functions. timer 0 and 1 can be configured by program to implement a 32 bit timer. the watchdog function can be activated either with timer 0 or timer 1 or both together (32 bit timer). in addition, the 83c154 has 2 software-selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the ram is saved, and the timers, the serial port and the interrupt system continue to function. in the power down mode the ram is saved and the timers, serial port and interrupt continue to function when driven by external clocks. in addition as for the temic 80c51/80c52, the stop clock mode is also available. the 80C154 is identical to the 83c154 except that it has no on-chip rom. temic's 80C154 and 83c154 are manufactured using scmos process which allows them to run from 0 up to 36 mhz with vcc = 5 v. 80C154 : romless version of the 83c154 m 80C154/83c154-12 : 0 to 12 mhz 80C154/83c154-16 : 0 to 16 mhz 80C154/83c154-20 : 0 to 20 mhz 80C154/83c154-25 : 0 to 25 mhz 80C154/83c154-30 : 0 to 30 mhz 80C154/83c154-36 : 0 to 36 mhz 80C154/83c154-l16 : low power version vcc : 2.7-5.5 v freq : 0-16 mhz for other speed and temperature range availability please consult your sales office. features power control modes 256 bytes of ram 16 kbytes of rom (83c154) 32 programmable i/o lines (programmable impedance) three 16 bit timer/counters (including watchdog and 32 bit timer) 64 k program memory space 64 k data memory space fully static design 0.8 m cmos process boolean processor 6 interrupt sources programmable serial port temperature range : commercial, industrial, automotive, military optional secret rom : encryption secret tag : identification number cmos 0 to 36 mhz single chip 8bit microcontroller
80C154/83c154 rev.f (14 jan. 97) 2 matra mhs interface figure 1. block diagram
80C154/83c154 rev.f (14 jan. 97) 3 matra mhs figure 2. pin configuration dil lcc flat pack 80C154/83c154 diagrams are for reference only. package sizes are not to scale 80C154/83c154 80C154/83c154 p1.4 p1.3 p1.2 p1.1/t2ex p1.0/t2 nc vcc p0.0/a0 p0.1/a1 p0.2/a2 p0.3/a3 p0.4/a4 p1.5 p1.6 p1.7 rst rxd/p3.0 nc txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 p0.5/a5 p0.6/a6 p0.7/a7 ea nc ale psen p2.7/a14 p2.6/a13 p2.5/a12 wr/p3.6 rd/p3.7 xtal2 xtal1 vss nc a7/p2.0 a8/p2.1 a9/p2.2 a10/p2.3 a11/p2.4 15 p 16 p 17 p 30 rxd/p 31 txd/p 32 int0/p 33 int1/p 34 t0/p 35 t1/p 36 wr/p 37 rd/p xtal2 xtal1 ss v nc 20 p 21 p 22 p 23 p 24 p rst nc 14 p 13 p 12 p 11 p 10 p nc cc v 0 a0/p /a8 /a9 /a10 /a11 /a12 04 p /a4 05 p /a5 06 p /a6 07 p /a7 ea nc ale psen 27 p /a15 26 p /a14 25 p /a13 /t2ex /t2 01 a1/p 02 a2/p 03 a3/p
80C154/83c154 rev.f (14 jan. 97) 4 matra mhs pin description vss circuit ground potential. vcc supply voltage during normal, idle, and power down operation. port 0 port 0 is an 8 bit open drain bi-directional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullups when emitting 1's. port 0 also outputs the code bytes during program verification in the 83c154. external pullups are required during program verification. port 0 can sink eight ls ttl inputs. port 1 port 1 is an 8 bit bi-directional i/o port with internal pullups. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil, on the data sheet) because of the internal pullups. port 1 also receives the low-order address byte during program verification. in the 83c154, port 1 can sink or source three ls ttl inputs. it can drive cmos inputs without external pullups. 2 inputs of port 1 are also used for timer/counter 2 : p1.0 [t2] : external clock input for timer/counter 2. p1.1 [t2ex] : a trigger input for timer/counter 2, to be reloaded or captured causing the timer/counter 2 interrupt. port 2 port 2 is an 8 bit bi-directional i/o port with internal pullups. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (ill, on the data sheet) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses (movx @dptr). in this application, it uses strong internal pullups when emitting 1's. during accesses to external data memory that use 8 bit addresses (movx @ri), port 2 emits the contents of the p2 special function register. it also receives the high-order address bits and control signals during program verification in the 83c154. port 2 can sink or source three ls ttl inputs. it can drive cmos inputs without external pullups. port 3 port 3 is an 8 bit bi-directional i/o port with internal pullups. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (ill, on the data sheet) because of the pullups. it also serves the functions of various special features of the temic 51 family, as listed below. port pin alternate function p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 rxd (serial input port) txd (serial output port) int0 (external interrupt 0) int1 (external interrupt 1) td (timer 0 external input) t1 (timer 1 external input) wr (external data memory write strobe) rd (external data memory read strobe) port 3 can sink or source three ls ttl inputs. it can drive cmos inputs without external pullups. rst a high level on this for two machine cycles while the oscillator is running resets the device. an internal pull-down resistor permits power-on reset using only a capacitor connected to vcc. as soon as the result is applied (vin), port 1, 2 and 3 are tied to 1. this operation is achieved asynchronously even if the oscillator is not start up.
80C154/83c154 rev.f (14 jan. 97) 5 matra mhs ale address latch enable output for latching the low byte of the address during accesses to external memory. ale is activated as though for this purpose at a constant rate of 1/6 the oscillator frequency except during an external data memory access at which time one ale pulse is skipped. ale can sink or source 8 ls ttl inputs. it can drive cmos inputs without an external pullup. psen program store enable output is the read strobe to external program memory. psen is activated twice each machine cycle during fetches from external program memory. (however, when executing out of external program memory, two activations of psen are skipped during each access to external data memory). psen is not activated during fetches from internal program memory. psen can sink/source 8 ls ttl inputs. it can drive cmos inputs without an external pullup. ea when ea is held high, the cpu executed out of internal program memory (unless the program counter exceeds 3fffh). when ea is held low, the cpu executes only out of external program memory. ea must not be floated. xtal1 input to the inverting amplifier that forms the oscillator. receives the external oscillator signal when an external oscillator is used. xtal2 output of the inverting amplifier that forms the oscillator, and input to the internal clock generator. this pin should be floated when an external oscillator is used. idle and power down operation figure 3 shows the internal idle and power down clock configuration. as illustrated, power down operation stops the oscillator. the interrupt, serial port, and timer blocks continue to function only with external clock (int0, int1, t0, t1). figure 3. idle and power down hardware. idle mode operation allows the interrupt, serial port, and timer blocks to continue to function with internal or external clocks, while the clock to cpu is gated off. the special modes are activated by software via the special function register, pcon. its hardware address is 87h. pcon is not bit addressable.
80C154/83c154 rev.f (14 jan. 97) 6 matra mhs pcon : power control register (msb) (lsb) smod hpd rpd gf1 gf0 pd idl symbol position name and function smod pcon.7 double baud rate bit. when set to a 1, the baud rate is doubled when the serial port is being used in either modes 1, 2 or 3. hpd pcon.6 hard power down bit. setting this bit allows cpu to enter in power down state on an external event (1 to 0 transition) on bit t1 (p. 3.5) the cpu quit the hard power down mode when bit t1 p. 3.5) goes high or when reset is activated. rpd pcon.5 recover from idle or power down bit. when 0 rpd has no effetc. when 1, rpd permits to exit from idle or power down with any non enabled interrupt source (except time 2). in this case the program start at the next address. when interrupt is enabled, the appropriate interrupt routine is serviced. gf1 pcon.3 general-purpose flag bit. gf0 pcon.2 general-purpose flag bit. pd pcon.1 power down bit. setting this bit activates power down operation. idl pcon.0 idle mode bit. setting this bit activates idle mode operation. if 1's are written to pd and idl at the same time. pd takes, precedence. the reset value of pcon is (000x0000). idle mode the instruction that sets pcon.0 is the last instruction executed before the idle mode is activated. once in the idle mode the cpu status is preserved in its entirety : the stack pointer, program counter, program status word, accumulator, ram and all other registers maintain their data during idle. in the idle mode, the internal clock signal is gated off to the cpu, but interrupt, timer and serial port functions are maintained. table 1 describes the status of the external pins during idle mode. there are three ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, terminating idle mode. the interrupt is serviced, and following reti, the next instruction to be executed will be the one following the instruction that wrote 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle mode is with a hardware reset. since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation. the third way to terminate the idle mode is the activation of any disabled interrupt when recover is programmed (rpd = 1). this will cause pcon.0 to be cleared. no interrupt is serviced. the next instruction is executed. if interrupt are disabled and rpd = 0, only a reset can cancel the idle mode. power down mode the instruction that sets pcon.1 is the last executed prior to entering power down. once in power down, the oscillator is stopped. the contents of the onchip ram and the special function register is saved during power down mode. the three ways to terminate the power down mode are the same than the idle mode. but since the onchip oscillator is stopped, the external interrupts, timers and serial port must be sourced by external clocks only, via int0, int1, t0, t1. in the power down mode, vcc may be lowered to minimize circuit power consumption. care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which frees the oscillator. reset should not be released until the oscillator has restarted and stabilized. when using voltage reduction : interrupt, timers and serial port functions are guaranteed in the vcc specification limits. table 1 describes the status of the external pins while in the power down mode. it should be noted that if the power down mode is activated while in external program memory, the port data that is held in the special function register p2 is restored to port 2. if the port switches from 0 to 1, the port pin is held high during the power down mode by the strong pullup, t1, shown in figure 4.
80C154/83c154 rev.f (14 jan. 97) 7 matra mhs table 1. status of the external pins during idle and power down modes. mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 port data port data port data port data idle external 1 1 floating port data address port data power down internal 0 0 port data port data port data port data power down external 0 0 floating port data port data port data figure 4. i/o buffers in the 83c154 (ports 1, 2, 3). stop clock mode due to static design, the temic 83c154 clock speed can be reduced until 0 mhz without any data loss in memory or registers. this mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value. at 0 mhz, the power consumption is the same as in the power down mode. i/o ports the i/o drives for p1, p2, p3 of the 83c154 are impedance programmable. the i/o buffers for ports 1, 2 and 3 are implemented as shown in figure 4 . when the port latch contains 0, all pfets in figure 4 are off while the nfet is turned on. when the port latch makes a 0-to-1 transition, the nfet turns off. the strong pullup pfet, t1, turns on for two oscillator periods, pulling the output high very rapidly. as the output line is drawn high, pfet t3 turns on through the inverter to supply the ioh source current. this inverter and t3 form a latch which holds the 1 and is supported by t2. when port 2 is used as an address port, for access to external program of data memory, any address bit that contains a 1 will have his strong pullup turned on for the entire duration of the external memory access. when an i/o pin on ports 1, 2, or 3 is used as an input, the user should be aware that the external circuit must sink current during the logical 1-to-0 transition. the maximum sink current is specified as itl under the d.c. specifications. when the input goes below approximately 2 v, t3 turns off to save icc current. note, when returning to a logical 1, t2 is the only internal pullup that is on. this will result in a slow rise time if the user's circuit does not force the input line high. the input impedance of port 1, 2, 2 are programmable through the register iocon. the alf bit (iocon0) set all of the port 1, 2, 3 floating when a power down mode occurs. the p1hz, p2hz, p3hz bits (iocon1, iocon2, iocon3) set respectively the ports p1, p2, p3 in floating state. the izc (iocon4) allows to choose input impedance of all ports (p1, p2, p3). when izc = 0, t2 and t3 pullup of i/o ports are active ; the internal input impedance is approximately 10 k. when izc = 1 only t2 pull-up is active. the t3 pull-up is turned off by izc. the internal impedance is approximately 100 k. oscillator characteristics xtal1 and xtal2 are the input and output respectively, of an inverting amplifier which is configured for use as an on-chip oscillator, as shown in figure 5. either a quartz crystal or ceramic resonator may be used. figure 5. crystal oscillator. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected as shown in figure 6 . there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed.
80C154/83c154 rev.f (14 jan. 97) 8 matra mhs figure 6. external drive configuration. hardware description same as for the 80c51, plus a third timer/counter : timer/event counter 2 timer 2 is a 16 bit timer/counter like timers 0 and 1, it can operate either as a timer or as an event counter. this is selected by bit c/t2 in the special function register t2con (figure 1). it has three operating modes : acaptureo, aautoloado and abaud rate generatoro, which are selected by bits in t2con as shown in table 2 . table 2.timer 2 operating modes. rclk + tclk cp/rl2 tr2 mode 0 0 1 x 0 1 x x 1 1 1 0 16 bit auto-reload 16 bit capture baud rate generator (off) in the capture mode there are two options which are selected by bit exen2 in t2con; if exen2 = 0, then timer 2 is a 16 bit timer or counter which upon overflowing sets bit tf2, the timer 2 overflow bit, which can be used to generate an interrupt. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. the capture mode is illustrated in figure 7 . in the auto-reload mode there are again two options, which are selected by bit exen2 in t2con.if exen2 = 0, then when timer 2 rolls over it does not only set tf2 but also causes the timer 2 register to be reloaded with the 16 bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1, then timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16 bit reload and set exf2. the auto-reload mode is illustrated in figure 8 . figure 7. timer 2 in capture mode. figure 8. timer 2 in auto-reload mode.
80C154/83c154 rev.f (14 jan. 97) 9 matra mhs (msb) (lsb) tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 the baud rate generator mode is selected by : rclk = 1 and/or tclk = 1. symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk = 1 or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. rclk t2con.5 receive clock flag. when set, causes the serial port to use timer2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/12) 1 = external event counter (falling edge triggered). cp/rl2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen 2 = 1. when cleared, auto reloads will occur either with timer 2 overflows or negative transition at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. timer functions in fact, timer 0 & 1 can be connected by a software instruction to implement a 32 bit timer function. timer 0 (mode 3) or timer 1 (mode 0, 1, 2) or a 32 bit timer consisting of timer 0 + timer 1 can be employed in the watchdog mode, in which case a cpu reset is generated upon a tf1 flag. the internal pull-up resistances at ports 1~3 can be set to a ten times increased value simply by software. 32 bit mode and watching mode the 83c154 has two supplementary modes. they are accessed by bits wdt and t32 of register iocon. figure 10 showns how iocon must be programmed in order to have access to these functions figure 9. 32 bit timer [iocon bit 6 (t32) = 1] watchdog timer
80C154/83c154 rev.f (14 jan. 97) 10 matra mhs (msb) (lsb) wdt t32 serr izc p3hz p2hz p1hz alf symbol position name and significance t32 iocon.6 if t32 = 1 and if c/t0 = 0, t1 and t0 are programmed as a 32 bit timer. if t32 = 1 and if c/t0 = 1, t1 and t0 are programmed as a 32 bit counter. wdt iocon.7 if wdt = 1 and according to the mode selected by tmod, an 8 bit or 32 bit watchdog is configured from timers 0 and 1. 32 bit mode t32 = 1 enables access to this mode. as shown in figure 11, this 32 bit mode consists in cascading timer 0 for the lsbs and timer 1 for the msbs figure 10.32 bit timer/counter. t32 = 1 starts the timer/counter and t32 = 0 stops it. it should be noted that as soon as t32 = 0. timers 0 and 1 assume the configuration specified by register tmod. moreover, if tr0 = 1 or if tr1 = 1, the content of the timers evolves. consequently, in 32 bit mode, if the timer/counter muste be stopped (t32 = 0), tr0 and tr1 must be set to 0. 32 bit timer figure 12 illustrates the 32 bit timer mode. figure 11. 32 bit timer configuration. in this mode, t32 = 1 and c/t0 = 0, the 32 bit timer is incremented on each s3p1 state of each machine cycle. an overflow of timer 0 (tf0 has not been set to 1) increments timer 1 and the overflow of the 32 bit timer is signalled by setting tf1 (s5p1) to 1. the following formula should be used to calculate the required frequency :

80C154/83c154 rev.f (14 jan. 97) 11 matra mhs 32 bit counter figure 13 illustrates the 32 bit counter mode. figure 12. 32 bit counter configuration. in this mode, t32 = 0 and c/t0 = 1. before it can make an increment, the 83c154 m must detect two transitions on its t0 input. as shown in figure 14, input t0 is sampled on each s5p2 state of every machine cycle or, in other words, every osc 12. figure 13. counter incrementation condition. the counter will only evolve if a level 1 is detected during state s5p2 of cycle ci and if a level 0 is detected during state s5p2 of cycle ci + n. consequently, the minimal period of signal fext admissible by the counter must be greater than or equal to two machine cycles. the following formula should be used to calculate the operating frequency.

watchdog mode wdt = 1 enables access to this mode. as shown in figure 15, all the modes of timers 0 and 1, of which the overflows act on tf1 (tf1 = 1), activate the watchdog mode. figure 14. the different watchdog configurations.
80C154/83c154 rev.f (14 jan. 97) 12 matra mhs if c/t = 0, the watchdog is a timer that is incremented every machine cycle. if c/t = 1, the watchdog is a counter that is incremented by an external signal of which the frequency cannot exceed osc 24. the overflow of the timer/counter is signalled by raising flag tf1 to 1. the reset of the 83c154 is executed during the next machine cycle and lasts for the next 5 machine cycles. the results of this reset are identical to those of a hardware reset. the internal ram is not affected and the special register assume the values shown in table 3. table 3. content of the sfrs after a reset triggered by the watchdog. register content pc acc b psw sp dptr p0-p3 ip ie tmod tcon t2con th0 tl0 th1 tl1 th2 tl2 rcap2h rcap2l scon sbuf iocon pcon 000h 00h 00h 00h 07h 0000h 0ffh 0x000000b 0x000000b 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h indeterminate 00h 000x0000b as there are no precautions for protecting bit wdt from spurious writing in the iocon register, special care must be taken when writing the program. in particular, the user should use the iocon register bit handling instructions : setb and clr x in preference to the byte handling instructions : mov iocon, # xxh, orl iocon, #xxh, anl iocon, #xxh external counting in power-down mode (pd = pcon.1 = 1) in the power-down mode, the oscillator is turned off and the 83c154's activity is frozen. however, if an external clock is connected to one of the two inputs, t1/t0, timer/counters 0 and 1 can continue to operate. in this case, counting becomes asychronous and the maximum, admissible frequency of the signal is osc : 24. the overflow of either counter tf0 or tf1 causes an interrupt to be serviced or forces a reset if the counter is in the watchdog mode (t32 = icon.7 = 1).
80C154/83c154 rev.f (14 jan. 97) 13 matra mhs 83c154 with secret rom temic offers 83c154 with the encrypted secret rom option to secure the rom code contained in the 83c154 microcontrollers. the clear reading of the program contained in the rom is made impossible due to an encryption through several random keys implemented during the manufacturing process. the keys used to do such encryption are selected randomwise and are definitely different from one microcontroller to another. this encryption is activated during the following phases : everytime a byte is addressed during a verify of the rom content, a byte of the encryption array is selected. movc instructions executed from external program memory are disabled when fetching code bytes from internal memory. ea is sampled and latched on reset, thus all state modification are disabled. for further information please refer to the application note (anm053) available upon request. 83c154 with secret tag temic offers special 64-bit identifier called asecret tago on the microcontroller chip. the secret tag option is available on both romless and masked microcontrollers. the secret tag feature allows serialization of each microcontroller for identification of a specific equipment. a unique number per device is implemented in the chip during manufacturing process. the serial number is a 64-bit binary value which is contained and addressable in the special function registers (sfr) area. this secret tag option can be read-out by a software routine and thus enables the user to do an individual identity check per device. this routine is implemented inside the microcontroller rom memory in case of masked version which can be kept secret (and then the value of the secret tag also) by using a rom encryption. for further information, please refer to the application note (anm031) available upon request.
80C154/83c154 rev.f (14 jan. 97) 14 matra mhs electrical characteristics absolute maximum ratings* ambiant temperature under bias : c = commercial 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i = industrial 40 c to +85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 c to + 150 c . . . . . . . . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . . . . . . . . . . . . . power dissipation 1 w** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ** this value is based on the maximum allowable die temperature and the thermal resistance of the package * notice stresses at or above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. dc parameters ta = 0 c to 70 c ; vcc = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz ta = 40 c + 85 c ; vcc = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.3 0.45 1.0 v v v iol = 100 m a iol = 1.6 ma (note 2) iol = 3.5 ma vol1 output low voltage (port 0, ale, psen ) 0.3 0.45 1.0 v v v iol = 200 m a iol = 3.2 ma (note 2) iol = 7.0 ma voh output high voltage port 1, 2 and 3 vcc 0.3 v ioh = 10 m a vcc 0.7 v ioh = 30 m a vcc 1.5 v ioh = 60 m a vcc = 5 v 10 % voh1 output high voltage (port 0, ale, psen ) vcc 0.3 v ioh = 200 m a vcc 0.7 v ioh = 3.2 ma vcc 1.5 v ioh = 7.0 ma vcc = 5 v 10 % iil logical 0 input current (ports 1, 2 and 3) 50 m a vin = 0.45 v ili input leakage current +/ 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 650 m a vin = 2.0 v ipd power down current 50 m a vcc = 2.0 v to 5.5 v (note 1) rrst rst pulldown resistor 50 200 kohm cio capacitance of i/o buffer 10 pf fc = 1 mhz, ta = 25 c icc power supply current freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 12 mhz icc op = 1.3 freq (mhz) + 4.5 ma icc idle = 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc = 5.5 v
80C154/83c154 rev.f (14 jan. 97) 15 matra mhs absolute maximum ratings* ambient temperature under bias : a = automotive 40 c to +125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 c to + 150 c . . . . . . . . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ** this value is based on the maximum allowable die temperature and the thermal resistance of the package * notice stresses at or above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. dc parameters ta = 40 c + 125 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.3 0.45 1.0 v iol = 100 m a iol = 1.6 ma (note 2) iol = 3.5 ma vol1 output low voltage (port 0, ale, psen ) 0.3 0.45 1.0 v iol = 200 m a iol = 3.2 ma (note 2) iol = 7.0 ma voh output high voltage port 1, 2 and 3 vcc 0.3 v ioh = 10 m a vcc 0.7 v ioh = 30 m a vcc 1.5 v ioh = 60 m a vcc = 5 v 10 % voh1 output high voltage (port 0, ale, psen ) vcc 0.3 v ioh = 200 m a vcc 0.7 v ioh = 3.2 ma vcc 1.5 v ioh = 7.0 ma vcc = 5 v 10 % iil logical 0 input current (ports 1, 2 and 3) 50 m a vin = 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 750 m a vin = 2.0 v ipd power down current 75 m a vcc = 2.0 v to 5.5 v (note 1) rrst rst pulldown resistor 50 200 kohm cio capacitance of i/o buffer 10 pf fc = 1 mhz, ta = 25 c icc power supply current freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 12 mhz icc op = 1.3 freq (mhz) + 4.5 ma icc idle = 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc = 5.5 v
80C154/83c154 rev.f (14 jan. 97) 16 matra mhs absolute maximum ratings* ambient temperature under bias : m = military 55 c to +125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 c to + 150 c . . . . . . . . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ** this value is based on the maximum allowable die temperature and the thermal resistance of the package * notice stresses at or above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. dc parameters ta = 55 c + 125 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 vcc + 0.5 v vih1 input high voltage (for xtal and rst) 0.7 vcc vcc + 0.5 v vol output low voltage (port 1, 2 and 3) 0.45 v iol = 1.6 ma (note 2) vol1 output low voltage (port 0, ale, psen) 0.45 v iol = 3.2 ma (note 2) voh output high voltage (port 1, 2, 3) 2.4 v ioh = 60 m a vcc = 5 v 10 % 0.75 vcc v ioh = 25 m a 0.9 vcc v ioh = 10 m a voh1 output high voltage (port 0 in external bus mode, ale, pen) 2.4 v ioh = 400 m a vcc = 5 v 10 % 0.75 vcc v ioh = 150 m a 0.9 vcc v ioh = 40 m a iil logical 0 input current (ports 1, 2 and 3) 75 m a vin = 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2 and 3) 750 m a vin = 2.0 v ipd power down current 75 m a vcc = 2.0 v to 5.5 v (note 1) rrst rst pulldown resistor 50 200 koh m cio capacitance of i/o buffer 10 pf fc = 1 mhz, ta = 25 c icc power supply current freq = 1 mhz icc op icc idle freq = 6 mhz icc op icc idle freq 12 mhz icc op = 1.3 freq (mhz) + 4.5 ma icc idle = 0.36 freq (mhz) + 2.7 ma 1.8 1 10 4 ma ma ma ma vcc = 5.5 v
80C154/83c154 rev.f (14 jan. 97) 17 matra mhs absolute maximum ratings* ambient temperature under bias : c = commercial 0 c to +70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i = industrial 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65 c to + 150 c . . . . . . . . . . . . . . . . . . . . . . . . voltage on vcc to vss 0.5 v to + 7 v . . . . . . . . . . . . . . . . . . . . . . . . voltage on any pin to vss 0.5 v to vcc + 0.5 v . . . . . . . . . . . . . . . power dissipation 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ** this value is based on the maximum allowable die temperature and the thermal resistance of the package * notice stresses at or above those listed under a absolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. dc parameters ta = 0 c to 70 c ; vcc = 2.7 v to 5.5 v ; vss = 0 v ; f = 0 to 16 mhz ta = 40 c to 85 c ; vcc = 2.7 v to 5.5 v symbol parameter min max unit test conditions vil input low voltage 0.5 0.2 vcc 0.1 v vih input high voltage (except xtal and rst) 0.2 vcc + 1.4 v vcc + 0.5 v vih1 input high voltage to xtal1 0.7 vcc vcc + 0.5 v vih2 input high voltage to rst for reset 0.7 vcc vcc + 0.5 v vpd power down voltage to vcc in pd mode 2.0 6.0 v vol output low voltage (ports 1, 2, 3) 0.45 v iol = 0.8 ma (note 2) vol1 output low voltage port 0, ale, psen 0.45 v iol = 1.6 ma (note 2) voh output high voltage ports 1, 2, 3 0.9 vcc v ioh = 10 m a voh1 output high voltage (port 0 in external bus mode), ale, psen 0.9 vcc v ioh = 40 m a iil logical 0 input current ports 1, 2, 3 50 m a vin = 0.45 v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current (ports 1, 2, 3) 650 m a vin = 2.0 v ipd power down current 50 m a vcc = 2 v to 5.5 v (note 1) rrst rst pulldown resistor 50 200 k w cio capacitance of i/o buffer 10 pf fc = 1 mhz, t a = 25 c maximum icc (ma) operating (note 1) idle (note 1) frequency/vcc 2.7 v 3 v 3.3 v 5.5 v 2.7 v 3 v 3.3 v 5.5 v 1 mhz 0.8 ma 1 ma 1.1 ma 1.8 ma 400 m a 500 m a 600 m a 1 ma 6 mhz 4 ma 5 ma 6 ma 10 ma 1.5 ma 1.7 ma 2 ma 4 ma 12 mhz 8 ma 10 ma 12 ma 2.5 ma 3 ma 3.5 ma 16 mhz 10 ma 12 ma 14 ma 3 ma 3.8 ma 4.5 ma freq > 12 mhz (vcc = 5.5 v) icc (ma) = 1.3 freq (mhz) + 4.5 icc idle (ma) = 0.36 freq (mhz) + 2.7
80C154/83c154 rev.f (14 jan. 97) 18 matra mhs note 1 : icc is measured with all output pins disconnected ; xtal1 driven with tclch, tchcl = 5 ns, vil = vss + .5 v, vih = vcc .5 v ; xtal2 n.c. ; ea = rst = port 0 = vcc. icc would be slighty higher if a crystal oscillator used. idle icc is measured with all otput pins disconnected ; xtal1 driven with tclch, tchcl = 5 ns, vil = vss + 5 v, vih = vcc -.5 v ; xtal2 n.c ; port 0 = vcc ; ea = rst = vss. power down icc is measured with all output pins disconnected ; ea = port 0 = vcc ; xtal2 n.c. ; rst = vss. note 2 : capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations. in the worst cases (capacitive loading 100 pf), the noise pulse on the ale line may exceed 0.45 v may exceed 0,45 v with maxi vol peak 0.6 v a schmitt trigger use is not necessary. figure 15. icc test condition, idle mode. all other pins are disconnected. figure 16. icc test condition, active mode. all other pins are disconnected. figure 17. icc test condition, power down mode. all other pins are disconnected. figure 18. clock signal waveform for icc tests in active and idle modes. tclch = tchcl = 5 ns.
80C154/83c154 rev.f (14 jan. 97) 19 matra mhs explanation of the ac symbol each timing symbol has 5 characters. the first character is always a ato (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example : tavll = time for address valid to ale low. tllpl = time for ale low to psen low. a : address. c : clock. d : input data. h : logic level high i : instruction (program memory contents). l : logic level low, or ale. p : psen. q : output data. r : read signal. t : time. v : valid. w : write signal. x : no longer a valid logic level. z : float. ac parameters ta = 0 to + 70 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz ta = 55 + 125 c ; vss = 0 v ; 2.7 v < vcc < 5.5 v ; f = 0 to 16 mhz ta = 55 + 125 c ; vss = 0 v ; vcc = 5 v 10 % ; f = 0 to 36 mhz (load capacitance for port 0, ale and psen = 100 pf ; load capacitance for all other outputs = 80 pf) external program memory characteristics 16 mhz 20 mhz 25 mhz 30 mhz 36 mhz symbol parameter min max min max min max min max min max tlhll ale pulse width 110 90 70 60 50 tavll address valid to ale 40 30 20 15 10 tllax address hold after ale 35 35 35 35 35 tlliv ale to valid instr in 185 170 130 100 80 tllpl ale to psen 45 40 30 25 20 tplph psen pulse width 165 130 100 80 75 tpliv psen to valid instr in 125 110 85 65 50 tpxix input instr hold after psen 0 0 0 0 0 tpxiz input instr float after psen 50 45 35 30 25 tpxav psen to address valid 55 50 40 35 30 taviv address to valid instr in 230 210 170 130 90 tplaz psen low to address float 10 10 8 6 5 external program memory read cycle taviv
80C154/83c154 rev.f (14 jan. 97) 20 matra mhs external data memory characteristics 16 mhz 20 mhz 25 mhz 30 mhz 36 mhz symbol parameter min max min max min max min max min max trlrh rd pulse width 340 270 210 180 120 twlwh wr pulse width 340 270 210 180 120 tllax address hold after ale 85 85 70 55 35 trldv rd to valid in 240 210 175 135 110 trhdx data hold after rd 0 0 0 0 0 trhdz data float after rd 90 90 80 70 50 tlldv ale to valid data in 435 370 350 235 170 tavdv address to valid data in 480 400 300 260 190 tllwl ale to wr or rd 150 250 135 170 120 130 90 115 70 100 tavwl address to wr or rd 180 180 140 115 75 tqvwx data valid to wr transition 35 35 30 20 15 tqvwh data setup to wr transition 380 325 250 215 170 twhqx data hold after wr 40 35 30 20 15 trlaz rd low to address float 0 0 0 0 0 twhlh rd or wr high to ale high 35 90 35 60 25 45 20 40 20 40 external data memory write cycle tavwl tqvwx external data memory read cycle
80C154/83c154 rev.f (14 jan. 97) 21 matra mhs serial port timing shift register mode 16 mhz 20 mhz 25 mhz 30 mhz 36 mhz symbol parameter min max min max min max min max min max txlxl serial port clock cycle time 750 600 480 400 330 tqvxh output data setup to clock rising edge 563 480 380 300 220 txhqx output data hold after clock rising edge 63 90 65 50 45 txhdx input data hold after clock rising edge 0 0 0 0 0 txhdv clock rising edge to input data valid 563 450 350 300 250 shift register timing waveforms
80C154/83c154 rev.f (14 jan. 97) 22 matra mhs external clock drive characteristics (xtal1) symbol parameter min max unit fclcl oscillator frequency 36 mhz tclcl oscillator period 27.8 ns tchcx high time 5 ns tclcx low time 5 ns tclch rise time 5 ns tchcl fall time 5 ns external clock drive waveforms ac testing input/output waveforms ac inputs during testing are driven at vcc 0.5 for a logic a1o and 0.45 v for a logic a0o. timing measurements are made at vih min for a logic a1o and vil max for a logic a0o. float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded voh/vol level occurs. iol/ioh 20 ma.
80C154/83c154 rev.f (14 jan. 97) 23 matra mhs clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a = 25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications.
80C154/83c154 rev.f (14 jan. 97) 24 matra mhs ordering information temperature range blank : commercial i : industrial a : automotive m : military part number 83c154 rom 16 k 8 80C154 external rom 83c154c secret rom version 83c154t secret tag version customer rom code i 83c154c 12 : 12 mhz version 16 : 16 mhz version 20 : 20 mhz version 25 : 25 mhz version 30 : 30 mhz version 36 : 36 mhz version l16 : low power (vcc : 2.7-5.5 v freq : 0-16 mhz) r : tape and reel d : dry pack package type p: pdil 40 s: plcc 44 f1: pqfp 44 (foot print 13.9 mm) f2: pqfp 44 (foot print 12.3 mm) v: vqfp (1.4 mm) t: tqfp (1.0 mm) d: cdil 40 q: cqfp 44 r: lcc 44 flow /883: mil 883 compliant p883: mil 883 compliant with pind test.

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